Turbo codes are based on parallel concatenation of two recursive systematic convolutional codes separated by an interleaves. Similar to gas in a turbo-compressed engine that is constantly recycled during operation, turbo coding algorithms uses an iterative algorithm between two decoders, constantly exchanging information between each other in order to improve error correction performance. Turbo coding is also used with concatenation of block codes. Turbo coding may be a channel coding scheme used in wireless broadcasting, communications, and networking standards. Some modern standards include, for example, CDMA2000 (Code Division Multiple Access 2000), DVB-SH (Digital Video Broadcasting-Satellite services to Handhelds), UMTS (Universal Mobile Telecommunications System), ETSI-SDR (European Telecommunications Standards Institute-Satellite Digital Radio), MediaFLO (Forward Link Only) and WiMax (Worldwide Interoperability for Microwave Access, IEEE 802.16). Turbo decoders are regularly implemented in dedicated hardware in, for example, various communications devices that receive encoded data. During regular operation, turbo decoders may become very computation-intensive and memory-intensive, both due to the memory used to store the received data sequence, and the number of iterations used to correct the received data. When operating to adhere to a specific standard (e.g., ETSI-SDR), the interleave address generation components of the turbo decoder may be implemented in dedicated hardware. When one standard needs to be supported, the interleave address generation can also be implemented in dedicated hardware. In this case, a range of block sizes need to be supported but the calculations remain largely the same. As the bit rate supported by the wireless standards increases, higher throughput turbo decoders are needed. New broadcast standards, such as DVB-SH, can require over 30 Mbps throughput for a single channel. When multiple channels are involved, the throughput can be well over 50 Mbps. Data rates higher than 100 Mbps are expected to be use in the near future. Efforts to achieve the constantly increasing throughput demands may require, for example, prohibitively high clock rates or separate, dedicated, fast clocks for the turbo decoder. Either implementation, however, may bring disadvantages, such as, for example, problems in the system-on-chip design for broadcast reception.
Turbo decoders are discussed by Wang, et al. in “Area-Efficient High-Speed Decoding Schemes for Turbo Decoders”, IEEE Transactions on VLSI Systems, vol. 10, no. 6 (December 2002) and by Boutillon, et al. in “Iterative Decoding of Concatenated Convolutional Codes: Implementation Issues”, Proceedings of the IEEE, vol. 95, no. 6 (June 2007).
Some implementations of the turbo decoder may use a number of parallel soft-in soft-out (SISO) decoders to process more data sequences simultaneously, thus creating a higher throughput without increasing the clock speed. However, the architecture of a turbo decoder may be heavily affected by the interleaver design specified in the communications standard. Some communications standards (such as UMTS LTE) may allow parallel processing much more readily than other standards, where, for example, the interleaving algorithm does not scale linearly, in which case design modifications are needed to assure parallel operation.
The turbo interleaver specified in the DVB-SH and ETSI-SDR standards is essentially not a parallel interleaver, meaning the turbo decoder will be implemented with a single SISO unit, limiting the throughput of the turbo decoder with the clock speed it runs at (e.g. for 200 MHz clock speed, less than 15 Mbps). However, higher throughputs are often required. This can be achieved by including multiple turbo decoders in the system, but that disadvantageously increases (e.g. doubles, triples) the silicon area needed for the turbo decoder.
In view of the foregoing, it would be desirable to implement a turbo decoder implementing parallel processing for a plurality of different communications standards that do not enable parallel processing.